PXS20RM Datasheet, PDF (919/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
28.5.1.3 Unique Vector for Each Interrupt Request Source
Each peripheral and software settable interrupt request is assigned a hardwired unique 9-bit vector.
Software settable interrupts 0 - 7 are assigned vectors 0 - 7 respectively. The peripheral interrupt requests
are assigned vectors 8 to as high as needed to cover all of the peripheral interrupt requests.
28.5.2 Priority Management
The asserted interrupt requests are compared to each other based on their PRIx values set in INTC_PSRn.
The result of that comparison also is compared to PRI in the associated INTC_CPR_PRC0 register. The
results of those comparisons are used to manage the priority of the ISR being executed by the associated
processor. The associated LIFO also assists in managing that priority.
28.5.2.1 Current Priority and Preemption
The priority arbitrator, selector, encoder, and comparator subblocks shown in Figure 28-1 are used to
compare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted
peripheral or software settable interrupt request is higher than the current priority for a given processor,
then the interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral
or software settable interrupt request is generated for the associated INTC_IACKR_PRC0 register, and if
in hardware vector mode, for the interrupt vector provided to the processor.
28.5.2.1.1 Priority Arbitrator Subblock
The priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt
requests assigned to that processor, both peripheral and software settable. The output of the priority
arbitrator subblock is the highest of those priorities assigned to a given processor. Also, any interrupt
requests which have this highest priority are output as asserted interrupt requests to the associated request
selector subblock.
28.5.2.1.2 Request Selector Subblock
If only one interrupt request from the associated priority arbitrator subblock is asserted, then it is passed
as asserted to the associated vector encoder subblock. If multiple interrupt requests from the associated
priority arbitrator subblock are asserted, then only the one with the lowest vector is passed as asserted to
the associated vector encoder subblock. The lower vector is chosen regardless of the time order of the
assertions of the peripheral or software settable interrupt requests.
28.5.2.1.3 Vector Encoder Subblock
The vector encoder subblock generates the unique 9-bit vector for the asserted interrupt request from the
request selector subblock for the associated processor.
28.5.2.1.4 Priority Comparator Subblock
The priority comparator subblock compares the highest priority output from the associated priority
arbitrator subblock with PRI in the associated INTC_CPR_PRC0. If the priority comparator subblock
detects that this highest priority is higher than the current priority, then it asserts the interrupt request to
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
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