PXS20RM Datasheet, PDF (228/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Generation Module (MC_CGM)
11.3.1.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC)
Address 0xC3FE_0390
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
W
SELCTL
0
0
0
0
0
0
0
0
Reset 0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-11. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC)
This register is used to select the current clock source for the following clocks:
• undivided: (unused)
• divided by auxiliary clock 2 divider 0: FlexCAN clock
Table 11-11. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) Field Descriptions
Field
Description
SELCTL Auxiliary Clock 2 Source Selection Control — This value selects the current source for auxiliary clock 2.
0000 reserved
0001 reserved
0010 reserved
0011 reserved
0100 system FMPLL
0101 secondary (120 MHz) FMPLL
0110 reserved
0111 reserved
1000 secondary (80 MHz) FMPLL
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
11.3.1.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)
Address0xC3FE_0394
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
R
0
0
0
DE0
W
DIV0
Reset
1
0
0
0
0
0
0
0
Figure 11-12. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)
This register controls the auxiliary clock 2 divider.
11-14
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor