PXS20RM Datasheet, PDF (339/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Table 16-11. DSPI_SR field descriptions (continued)
Field
Description
SPEF
(on cut2/3
only)
SPI Parity Error Flag. The SPEF flag indicates that a SPI frame with parity error had been received.
The bit remains set until cleared by writing 1 to it.
0 Parity Error has not occurred
1 Parity Error has occurred
RFOF
Receive FIFO Overflow Flag. The RFOF bit indicates that an overflow condition in the RX FIFO has
occurred. The bit is set when the RX FIFO and shift register are full and a transfer is initiated. The bit
remains set until cleared by writing 1 to it.
0 RX FIFO overflow has not occurred
1 RX FIFO overflow has occurred
RFDF
Receive FIFO Drain Flag. The RFDF bit provides a method for the DSPI to request that entries be
removed from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
cleared by writing 1 to it or by acknowledgement from the DMA controller when the RX FIFO is empty.
0 RX FIFO is empty
1 RX FIFO is not empty
TXCTR
TX FIFO Counter. The TXCTR field indicates the number of valid entries in the TX FIFO. The TXCTR
is incremented every time the DSPI _PUSHR is written. The TXCTR is decremented every time a SPI
command is executed and the SPI data is transferred to the shift register.
TXNXTPTR Transmit Next Pointer. The TXNXTPTR field indicates which TX FIFO Entry is transmitted during the
next transfer. The TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
the shift register. See Section 16.4.6.4, Transmit FIFO Underflow Interrupt Request, for more details.
RXCTR
RX FIFO Counter. The RXCTR field indicates the number of entries in the RX FIFO. The RXCTR is
decremented every time the DSPI _POPR is read. The RXCTR is incremented every time data is
transferred from the shift register to the RX FIFO.
POPNXTPTR Pop Next Pointer. The POPNXTPTR field contains a pointer to the RX FIFO entry that will be returned
when the DSPI_POPR is read. The POPNXTPTR is updated when the DSPI_POPR is read. See
Section 16.4.2.5, Receive First In First Out (RX FIFO) Buffering Mechanism, for more details.
16.3.2.6 DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER)
The DSPI_RSER register controls DMA and interrupt requests.
Do not write to the DSPI_RSER while the DSPI is in the Running state.
You are allowed to write to this register in Module Disable mode.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-19