PXS20RM Datasheet, PDF (809/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
Each receive shadow buffer consists of two parts, the physical message buffer located in the FlexRay
memory area and the receive shadow buffer control registers located in dedicated registers. The structure
of a receive shadow buffer is shown in Figure 26-115. The four internal shadow buffer control registers
can be accessed by the Receive Shadow Buffer Index Register (FR_RSBIR).
The connection between the receive shadow buffer control register and the physical message buffer for the
selected receive shadow buffer is established by the receive shadow buffer index field RSBIDX in the
Receive Shadow Buffer Index Register (FR_RSBIR). The start address SADR_MBHF of the related
message buffer header field in the FlexRay memory area is determined according to Equation 26-4.
SADR_MBHF = (FR_RSBIR[RSBIDX] * 10) + SMBA
Eqn. 26-4
The length required for the message buffer data field depends on the message buffer segment that the
receive shadow buffer is assigned to. For the receive shadow buffers assigned to the first message buffer
segment, the length must be the same as for the individual message buffers assigned to the first message
buffer segment. For the receive shadow buffers assigned to the second message buffer segment, the length
must be the same as for the individual message buffers assigned to the second message buffer segment.
The receive shadow buffer assignment is described in Receive Shadow Buffer Index Register
(FR_RSBIR).
(min) FR_MBDSR[MBSEG1DS] * 2 bytes / FR_MBDSR[MBSEG2DS] * 2 bytes
SADR_MBDF
Frame Data
Message Buffer Data Field
SADR_MBHF
Frame Header
Data Field Offset
Message Buffer Header Field
Slot Status
FR_RSBIDX[0]
FR_RSBIDX[1]
FR_RSBIDX[2]
FR_RSBIDX[3]
Receive Shadow Buffer Control Registers
Figure 26-115. Receive Shadow Buffer Structure
26.6.3.3 Receive FIFO
The receive FIFO implements a frame reception system based on the FIFO concept. The CC provides two
independent receive FIFOs, one per channel.
A receive FIFO consists of a set of physical message buffers in the FlexRay memory area and a set of
receive FIFO control registers located in dedicated registers. The structure of a receive FIFO is given in
Figure 26-116.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-97