PXS20RM Datasheet, PDF (863/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
NOTE
The values provided in the EOC_AP and ERC_AP fields are the values that
were written from the application most recently. If these value were already
applied, they will not be applied in the current cycle pair again.
If the offset correction applied in the NIT of cycle 2n+1 shall be affect by the external offset correction,
the EOC_AP field must be written to after the start of cycle 2n and before the end of the static segment of
cycle 2n+1. If this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed
that the external correction value is applied in cycle 2n+1. If the value is not applied in cycle 2n+1, then
the value will be applied in the cycle 2n+3. Refer to Figure 26-152 for timing details.
EOC_AP write window
EOC_AP application
static segment
cycle 2n
NIT
static segment
NIT
cycle 2n+1
Figure 26-152. External Offset Correction Write and Application Timing
If the rate correction for the cycle pair [2n+2, 2n+3] shall be affect by the external offset correction, the
ERC_AP field must be written to after the start of cycle 2n and before the end of the static segment start
of cycle 2n+1. If this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed
that the external correction value is applied in cycle pair [2n+2, 2n+3]. If the value is not applied for cycle
pair [2n+2, 2n+3], then the value will be applied for cycle pair [2n+4, 2n+5]. Refer to Figure 26-153 for
details.
ERC_AP write window
ERC_AP application
static segment
cycle 2n
NIT static segment
NIT static segment
NIT static segment
NIT
cycle 2n+1
cycle 2n+2
cycle 2n+3
Figure 26-153. External Rate Correction Write and Application Timing
26.6.12 Sync Frame ID and Sync Frame Deviation Tables
The FlexRay protocol requires the provision of a snapshot of the Synchronization Frame ID tables for the
even and odd communication cycle for both channels. The CC provides the means to write a copy of these
internal tables into the FlexRay memory area and ensures application access to consistent tables by means
of table locking. Once the application has locked the table successfully, the CC will not overwrite these
tables and the application can read a consistent snapshot.
NOTE
Only synchronization frames that have passed the synchronization frame
filters are considered for clock synchronization and appear in the sync frame
tables.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-151