PXS20RM Datasheet, PDF (677/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
— The filter detects a logic one on the FAULTx pin at the start of the next PWM full or half cycle
boundary. See Figure 25-30. If FFULLx is set, then the disabled PWM pins are enabled only
at the start of a full cycle and not at the half cycle.
COUNT
FFPINx BIT
OUTPUTS ENABLED DISABLED
ENABLED
FFLAGx
CLEARED
Figure 25-29. Manual Fault Clearing (FSAFE=0)
COUNT
FFPINx BIT
OUTPUTS
ENABLED DISABLED
ENABLED
FFLAGx
CLEARED
Figure 25-30. Manual Fault Clearing (FSAFE=1)
NOTE
Fault protection also applies during software output control when the
SEL23 and SEL45 fields are set to select OUT23 and OUT45 bits or EXTA
and EXTB. Fault clearing still occurs at half PWM cycle boundaries while
the PWM generator is engaged, RUN equals one. But the OUTx bits can
control the PWM pins while the PWM generator is off, RUN equals zero.
Thus, fault clearing occurs at IPBus cycles while the PWM generator is off
and at the start of PWM cycles when the generator is engaged.
25.3.3.11.4 Fault Testing
The FTEST bit is used to simulate a fault condition on each of the fault inputs.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
25-31