PXS20RM Datasheet, PDF (227/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Generation Module (MC_CGM)
Table 11-9. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) Field Descriptions
Field
Description
SELCT Auxiliary Clock 1 Source Selection Control — This value selects the current source for auxiliary
L clock 1.
0000 reserved
0001 reserved
0010 reserved
0011 reserved
0100 system FMPLL
0101 secondary (120 MHz) FMPLL
0110 reserved
0111 reserved
1000 secondary (80 MHz) FMPLL
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
11.3.1.8 Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)
Address0xC3FE_038C
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
R
0
0
0
DE0
W
DIV0
Reset
1
0
0
0
0
0
0
0
Figure 11-10. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)
This register controls the auxiliary clock 1 divider.
Table 11-10. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) field descriptions
Field
Description
DE0
DIV0
Divider 0 Enable
0 Disable auxiliary clock 1 divider 0
1 Enable auxiliary clock 1 divider 0
Divider 0 Division Value — The resultant FlexRay clock will have a period DIV0 + 1 times that of auxiliary
clock 1. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored and the
FlexRay clock remains disabled.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
11-13