PXS20RM Datasheet, PDF (332/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
16.3.2.4 DSPI Clock and Transfer Attributes Registers 0–3
(DSPI_CTAR0–DSPI_CTAR3)
The DSPI_CTAR registers are used to define different transfer attributes. Do not write to the DSPI_CTAR
registers while the DSPI is in the Running state.
In master mode, the DSPI_CTAR0 - DSPI_CTAR3 registers define combinations of transfer attributes
such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays.
In slave mode, a subset of the bitfields in the DSPI_CTAR0 and DSPI_CTAR1 registers are used to set the
slave transfer attributes.
When the DSPI is configured as a SPI master, the CTAS field in the command portion of the TX FIFO
entry selects which of the DSPI_CTAR register is used. When the DSPI is configured as a SPI bus slave,
the DSPI_CTAR0 register is used.
Address: DSPI_BASE + 0xC–DSPI_BASE + 0x18
0
1
R
DBR
W
Reset 0 1
2
3
FMSZ
11
4
5
6
7
8
9
CPOL CPHA LSBFE PCSSCK
10
0
0
00
10 11
PASC
00
12 13
PDT
00
Access:
14 15
PBR
00
16 17 18 19 20
R
CSSCK
W
21
22
ASC
23
24
25
26
27 28 29 30 31
DT
BR
Reset 0 0 0 0 0 0
0
0
0 0 0 00000
Figure 16-7. DSPI Clock and Transfer Attributes Register 0–3 (DSPI_CTAR0–DSPI_CTAR3) in master mode
Address: DSPI_BASE + 0xC /0x10
Access:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
000000000
FMSZ
CPOL CPHA
W
Reset 0 1 1 1 1
0
0
000000000
16
17
18
19
20
21
R0 0 0 0 0
0
22
23
24
25
26
27
28
29
30
31
0
0
000
00
0
00
W
Reset 0 0 0 0 0
0
0
000000000
Figure 16-8. DSPI Clock and Transfer Attributes Register 0, 1 (DSPI_CTAR0 for cut1, DSPI_CTAR1) in slave
mode
16-12
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor