PXS20RM Datasheet, PDF (623/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexCAN Module
Base + 0x001C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0000000000000000
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Rx_Err_Counter
W
Tx_Err_Counter
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 24-9. Error Counter Register (ECR)
24.3.4.8 Error and Status Register (ESR)
This register reflects various error conditions, some general status of the device and it is the source of four
interrupts to the CPU. The reported error conditions (bits 16-21) are those that occurred since the last time
the CPU read this register. The CPU read action clears bits 16-23. Bits 22-28 are status bits.
Most bits in this register are read only, except TWRN_INT, RWRN_INT, BOFF_INT, WAK_INT and
ERR_INT, that are interrupt flags that can be cleared by writing ‘1’ to them (writing ‘0’ has no effect). See
Section 24.4.10, Interrupts, for more details.
Base + 0x0020
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TWRN RWRN
_INT _INT
W
w1c w1c
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
16 17 18 19 20 21 22 23
R
BIT1_ BIT0_ ACK_ CRC_ FRM_ STF_ TX_W RX_
ERR ERR ERR ERR ERR ERR RN WRN
W
RESET: 0 0 0 0 0 0 0 0
24
IDLE
0
25
TXRX
0
26 27
FLT_CONF
00
28 29 30 31
0
BOFF ERR_ WAK_
_INT INT INT
w1c w1c w1c
00 0
0
= Unimplemented or Reserved
Figure 24-10. Error and Status Register (ESR)
TWRN_INT — Tx Warning Interrupt Flag
If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition
from ‘0’ to ‘1’, meaning that the Tx error counter reached 96. If the corresponding mask bit in the
Control Register (TWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by
writing it to ‘1’. Writing ‘0’ has no effect.
1 = The Tx error counter transition from < 96 to  96
0 = No such occurrence
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
24-23