PXS20RM Datasheet, PDF (379/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

e200z4d Core Complex Overview
17.3.1.2 Processor ID Register (PIR)
The processor ID for each of the two CPU cores is contained in its own Processor ID Register (PIR). The
contents of the PIR are a reflection of hardware input signals to the core following reset. This register may
be written by software to modify the default reset value. This register value can be used by the application
software to determine the core actually running the software.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0
CPUID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Core-dependent
Figure 17-5. Processor ID Register (PIR)
Table 17-2. PIR field descriptions
Field
CPUID
Processor ID
Description
17.3.1.3 System Version Register (SVR)
The SVR contains system version information for this device.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0
VER
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-6. System Version Register (SVR)
Table 17-3. SVR field descriptions
Field
VER
Device version
Description
17.3.2 Instruction set
The e200z4d supports the Power ISA instruction set for 32-bit embedded implementations. This is
composed primarily of the user-level instructions defined by the user instruction set architecture (UISA).
The e200z4d does not include the Power ISA floating-point, load string, or store string instructions.
The e200z4d core implements the following architectural extensions:
• The VLE category
• The integer select category (ISEL)
• Enhanced debug and the debug notify halt instruction categories
• The machine check category
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
17-9