PXS20RM Datasheet, PDF (855/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.6.9.2.1 Single System Memory Base Address Mode
This mode is configured, when the FIFO address mode flag FR_MCR[FAM] is set to 0. In this mode, the
location of the system memory base address for the FIFO buffers is System Memory Base Address
Register (FR_SYMBADR).
26.6.9.2.2 Dual System Memory Base Address Mode
This mode is configured, when the FIFO address mode flag FR_MCR[FAM] is set to 1. In this mode, the
location of the system memory base address for the FIFO buffers is Receive FIFO System Memory Base
Address Register (FR_RFSYMBADR).
The FIFO control and configuration data are given in Section 26.6.3.7, Receive FIFO Control and
Configuration Data. The configuration of the FIFOs consists of two steps.
The first step is the allocation of the required amount of memory for the FlexRay memory area. This
includes the allocation of the message buffer header area and the allocation of the message buffer data
fields. For more details see Section 26.6.4, FlexRay Memory Area Layout.
The second step is the programming of the configuration data register while the PE is in POC:config.
The following steps configure the layout of the FIFO.
• Configure the FIFO update and address modes in Module Configuration Register (FR_MCR)
• Configure the FIFO system memory base address
• Configure the Receive FIFO Start Index Register (FR_RFSIR) with the first message buffer header
index that belongs to the FIFO
• Configure the Receive FIFO Depth and Size Register (RFDSR) with FIFO entry size
• Configure the Receive FIFO Depth and Size Register (RFDSR) with FIFO depth
• Configure the FIFO Filters
26.6.9.3 FIFO Periodic Timer
The FIFO periodic timer is used to generate an FIFO almost-full interrupt at certain point in time, if the
almost-full watermark is not reached, but the FIFO is not empty. This can be used to prevent frames from
get stuck in the FIFO for a long time.
The FIFO periodic timer is configured via the Receive FIFO Periodic Timer Register (FR_RFPTR). If the
periodic timer duration FR_RFPTR[PTD] is configured to 0x0000, the periodic timer is continuously
expired. If the periodic timer duration FR_RFPTR[PTD] is configured to 0x3FFF, the periodic timer never
expires. If the periodic timer is configured to a value ptd, greater than 0x0000 and smaller 0x3FFF, the
periodic timer expires and is restarted at the start of every communication cycle, and expires and is
restarted after ptd macroticks have been elapsed.
26.6.9.4 FIFO Reception
The FIFO reception is a CC internal operation.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-143