PXS20RM Datasheet, PDF (481/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Table 21-8. MUDCR field descriptions
Field
Description
MUDCR
Platform RAM wait-state control
This bit is used to select whether the platform RAM controller will insert 1-wait state into every read
access made to the platform RAM arrays.
0 The platform RAM controller operates as a 0-wait state controller
1 The platform RAM controller operates as a 1-wait state controller
NOTE
In DPM, the chip has an additional ECSM (ECSM_1) that also contains a
MUDCR. Applications changing this configuration should take this fact
into account.
21.4.2.8 Platform ECC registers
There are a number of program-visible registers for the sole purpose of reporting and logging of memory
failures. These registers include the following:
• ECC Configuration Register (ECR)
• ECC Status Register (ESR)
• ECC Error Generation Register (EEGR)
• Platform Flash Memory ECC Address Register (PFEAR)
• Platform Flash Memory ECC Master Number Register (PFEMR)
• Platform Flash Memory ECC Attributes Register (PFEAT)
• Platform Flash Memory ECC Data Registers (PFEDRL and PFEDRH)
• Platform RAM ECC Address Register (PREAR)
• Platform RAM ECC Syndrome Register (PRESR)
• Platform RAM ECC Master Number Register (PREMR)
• Platform RAM ECC Attributes Register (PREAT)
• Platform RAM ECC Data Registers (PREDRL and PREDRH)
The details on the ECC registers are provided in the subsequent sections.
The 32-bit ECC organization essentially provides two completely independent error checking mechanisms
for the total 64-bit PRAM width. The ECC logic provides a 1-of-3 error response vector for each 32 bits
of memory: no error, single-bit correctable error, multi-bit non-correctable error. Table 21-9 defines the
association between the reported ECC result and the PRAM bank chip selects.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
21-7