PXS20RM Datasheet, PDF (1160/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Peripheral Bridge (PBRIDGE)
• Provides configurable per-peripheral access protections for both on-platform and off-platform
peripherals
37.4 Memory map and register description
37.4.1 Register access
All registers are 32-bit registers and can only be accessed in supervisor mode by trusted bus masters.
Additionally, these registers must only be read from or written to by a 32-bit aligned access.
Two system clock cycles are required for read accesses and three system clock cycles are required for write
accesses to the PBRIDGE registers.
37.4.2 Memory map
Each register in the PBRIDGE module has a size of 32 bits. The registers are listed in Table 37-1 . The
memory map organization is shown in Table 37-2. The organizational hierarchy is as follows:
• The module has multiple registers with the same register name (MPROT, PACR, OPACR), each at
a different address offset.
• Each register has multiple similarly-named fields, each with a different number.
• Each field has subfields as defined elsewhere in this section.
Accesses to registers or register fields marked as reserved will return undefined data on reads, and will be
ignored on writes.
Table 37-1. PBRIDGE registers
Offset from PBRIDGE_BASE
PBRIDGE0_0 = 0xFFF0_0000
PBRIDGE_1 = 0xFFF0_4000
Register
Access¹ Reset Value
Location
0x0000–0x0007 ²
Master Protection Registers (MPROT)
R/W
0x0008–0x001F
0x0020–0x003F ²
0x0040–0x006F ²
Reserved
Peripheral Access Control Registers
R/W
(PACR)
Off-Platform Peripheral Access Control R/W
Registers (OPACR)
0x0070–0x3FFF
Reserved
NOTES:
1 _{In this column, R/W = Read/Write, R = Read-only, and W = Write-only.}
2 _{This memory range contains reserved areas. See Table 37-2.}
3 _{See the associated description for more information.}
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on page 37-3
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on page 37-4
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on page 37-5
37-2
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor