PXS20RM Datasheet, PDF (950/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

JTAG Controller (JTAGC)
29.4.3.1 Enabling the TAP Controller
The JTAGC TAP controller is enabled by setting JCOMP to a logic 1 value.
29.4.3.2 Selecting an IEEE 1149.1-2001 Register
Access to the JTAGC data registers is achieved by loading the instruction register with any of the JTAGC
block instructions while the JTAGC is enabled. Instructions are shifted in via the Select-IR-Scan path and
loaded in the Update-IR state. At this point, all data register access is performed via the Select-DR-Scan
path.
The Select-DR-Scan path is used to read or write the register data by shifting in the data (LSB first) during
the Shift-DR state. When reading a register, the register value is loaded into the IEEE 1149.1-2001 shifter
during the Capture-DR state. When writing a register, the value is loaded from the IEEE 1149.1-2001
shifter to the register during the Update-DR state. When reading a register, there is no requirement to shift
out the entire register contents. Shifting may be terminated once the required number of bits have been
acquired.
29.4.4 JTAGC Block Instructions
The JTAGC block implements the IEEE 1149.1-2001 defined instructions listed in Table 29-3. This
section gives an overview of each instruction; refer to the IEEE 1149.1-2001 standard for more details. All
undefined opcodes are reserved.
Table 29-3. JTAG Instructions
Instruction
IDCODE
SAMPLE/PRELOAD
SAMPLE
EXTEST
ACCESS_AUX_TAP_x
Factory debug reserved
ACCESS_AUX_TAP_NPC
ACCESS_AUX_TAP_CORE_0
ACCESS_AUX_TAP_NXSS_LSM
ACCESS_AUX_TAP_NXSS_0
ACCESS_AUX_TAP_NXSS_1
ACCESS_AUX_TAP_CORE_1
ACCESS_AUX_TAP_LSM
Code[4:0]
00001
00010
00011
00100
10000-11110
00101, 00110,
01010, 00111
10000
10001
10110
10111
11000
11001
11010
Instruction Summary
Selects device identification register for shift
Selects boundary scan register for shifting, sampling, and
preloading without disturbing functional operation
Selects boundary scan register for shifting and sampling
without disturbing functional operation
Selects boundary scan register while applying preloaded
values to output pins and asserting functional reset
Grants one of the auxiliary TAP controllers ownership of
the TAP as shown in the cells below. The number of
auxiliary TAP controllers sharing the port is SHARE_CNT
Intended for factory debug only
Enables access to the NPC TAP controller
Enables access to Core_0 TAP controller only
Enables access to the NXSS modules in LSM (cut2/3
only)
Enables access to the NXSS_0 module (cut2/3 only)
Enables access to the NXSS_1 module (cut2/3 only)
Enables access to Core_1 TAP controller only
Enables access to Core TAP controllers in LS mode. Both
cores receive TDI input data.
29-10
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor