PXS20RM Datasheet, PDF (1285/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Semaphore Unit (SEMA4)
— if gate = 0b10, then state = locked by e200z4d_1 (master ID = 1)
— Uses the bus master ID number as a reference attribute plus the specified data patterns to
validate all write operations
— After it is locked, the gate must be unlocked by a write of zeroes from the locking processor
• Optionally enabled interrupt notification after a failed lock write provides a mechanism to indicate
the gate is unlocked
• Secure reset mechanisms are supported to clear the contents of individual semaphore gates or
notification logic, and clear_all capability
NOTE
Semaphore gates that are locked when entering sleep mode are cleared by
the internal reset generated when exiting sleep mode.
43.1.3 Modes of operation
The SEMA4 unit does not support any special modes of operation.
43.2 Signal description
The SEMA4 unit does not include any external signals.
43.3 Memory map and register description
The SEMA4 programming model map is shown in Table 43-1. The address of each register is given as an
offset to the SEMA4 base address. Registers are listed in address order, identified by complete name and
mnemonic, and list the type of accesses allowed.
Table 43-1. SEMA4 memory map
Address offset
Register
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
SEMA4_Gate00—Semaphores gate 0
SEMA4_Gate01—Semaphores gate 1
SEMA4_Gate02—Semaphores gate 2
SEMA4_Gate03—Semaphores gate 3
SEMA4_Gate04—Semaphores gate 4
SEMA4_Gate05—Semaphores gate 5
SEMA4_Gate06—Semaphores gate 6
SEMA4_Gate07—Semaphores gate 7
SEMA4_Gate08—Semaphores gate 8
SEMA4_Gate09—Semaphores gate 9
SEMA4_Gate10—Semaphores gate 10
SEMA4_Gate11—Semaphores gate 11
SEMA4_Gate12—Semaphores gate 12
Location
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Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
43-3