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e200z4d Core Complex Overview
Chapter 17
e200z4d Core Complex Overview
This chapter provides an overview of the e200z4d microprocessor core present in this device. It includes
the following:
• An overview of the core, including the block diagram (Figure 17-1)
• A summary of the feature set for this core (see Section 17.2, Features)
— A description of the execution units (see Section 17.2.1, Execution Unit Features)
— A description of the memory management architecture (see Section 17.2.3, Memory
Management Unit Features)
— High-level details of the external core compex interface (see Section 17.2.4, Exernal core
complex interface features)
— High-level details of the Nexus 3+ features (see Section 17.2.5, Nexus 3+ Features)
• A summary of the programming model for this core (see Section 17.3, Programming model)
— An overview of the register set (see Section 17.3.1, Register set)
— An overview of the instruction set (see Section 17.3.2, Instruction set)
— An overview of interrupts and exception handling (see Section 17.3.3, Interrupts and Exception
Handling)
• A summary of instruction pipeline and flow (see Section 17.4, Microarchitecture summary)
17.1 Overview
The e200z4d processor family is a set of CPU cores that implement low-cost versions of Power
Architecture technology. The e200z4d core is a dual-issue, 32-bit design with 64-bit general-purpose
registers (GPRs). The e200z4d integrates a CPU core, a memory management unit (MMU), a 4-Kbyte
instruction cache, and a Nexus Class 3+ real-time debug unit. Separate instruction and data AHB 2.v6
system interfaces are provided.
The e200z4d is compliant with the Power Architecture instruction set architecture (ISA). It does not
support Power Architecture ISA floating-point instructions in hardware, but traps them so they can be
emulated by software.
Instructions of the embedded floating-point category are provided to support real-time single-precision
embedded numerics operations using the general-purpose registers.
Instructions of the signal processing extension (SPE) category are provided to support real-time SIMD
fixed-point and single-precision embedded numerics operations using the general-purpose registers. All
arithmetic instructions that execute in the core operate on data in the general-purpose registers (GPRs).
The GPRs have been extended to 64-bits in order to support vector instructions defined by the SPE
category. These instructions operate on a vector pair of 16-bit or 32-bit data types and deliver vector and
scalar results.
In addition to the base Power Architecture ISA embedded category instruction set, the core also
implements the variable-length encoding category (VLE), which provides improved code density. See the
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
17-1