PXS20RM Datasheet, PDF (302/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Crossbar Switch (XBAR)
Name
MSTR_6
Table 15-7. Master Priority Register descriptions (continued)
Description
Settings
Master 6 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 6 on the associated slave port.
when accessing the slave port.
Bit 8
MSTR_5
Bit 12
MSTR_4
These bits are initialized by hardware reset.
The reset value is 110
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 5 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 5 on the associated slave port.
when accessing the slave port.
These bits are initialized by hardware reset.
The reset value is 101
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 4 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 4 on the associated slave port.
when accessing the slave port.
Bit 16
MSTR_3
These bits are initialized by hardware reset.
The reset value is 100
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 3 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 3 on the associated slave port.
when accessing the slave port.
Bit 20
MSTR_2
Bit 24
MSTR_1
These bits are initialized by hardware reset.
The reset value is 011
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 2 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 2 on the associated slave port.
when accessing the slave port.
These bits are initialized by hardware reset.
The reset value is 010
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 1 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 1 on the associated slave port.
when accessing the slave port.
Bit 28
These bits are initialized by hardware reset.
The reset value is 001
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
15-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor