PXS20RM Datasheet, PDF (296/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Crossbar Switch (XBAR)
NOTES:
1 _{DMA_1 is not enabled in DPM. LMID assigned here for completeness and future enhancements.}
2 _{The MPU cannot differentiate between core and Nexus accesses to slave ports.}
15.1.5 Master port allocation
Table 15-2 defines the XBAR master port allocation for this device.
Table 15-2. XBAR master port allocation
XBAR master
port
LSM
XBAR_0 module
XBAR_1 module
DPM
XBAR_0 module
XBAR_1 module
M0
z4d_0 core complex z4d_1 core complex z4d_0 core complex z4d_1 core complex
Instruction port
Instruction port
Instruction port
Instruction port
M1
z4d_0 core complex z4d_1 core complex z4d_0 core complex z4d_1 core complex
Load/Store port +
Load/Store port +
Load/Store port +
Load/Store port +
Nexus port
Nexus port
Nexus port
Nexus port
M2
DMA_0
DMA_1
DMA_0
DMA_1¹
M3
FlexRay
FlexRay
FlexRay
FlexRay
M4
—
—
—
—
M5
—
—
z4d_1 core complex z4d_0 core complex
Instruction port
Instruction port
M6
—
—
z4d_1 core complex z4d_0 core complex
Load/Store port +
Load/Store port +
Nexus port
Nexus port
M7
—
—
—
—
NOTES:
1 _{DMA_1 is not enabled in DPM. XBAR Master Port assigned here for completeness and future enhancements.}
15.1.6 Slave port allocation
Table 15-3 defines the XBAR slave port allocation for this device.
Table 15-3. XBAR slave port allocation
XBAR slave
port
S0
S1
S2
S3
LSM
DPM
XBAR_0 module
PFLASH_0_PORT_0
—
SRAMC_0
—
XBAR_1 module
PFLASH_1_PORT_1
—
SRAMC_1
—
XBAR_0 module
PFLASH_0_PORT_0
PFLASH_1_PORT_0
—
SRAMC_0
—
XBAR_1 module
PFLASH_0_PORT_1
PFLASH_1_PORT_1
—
SRAMC_1
—
15-2
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor