PXS20RM Datasheet, PDF (532/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Fault Collection and Control Unit (FCCU)
To guarantee the self checking capabilities through the FAULT interface, each critical fault source must be
duplicated on a couple of CF inputs.
Two separate IRCOSC clock inputs are routed to the redundant sub-modules (FSMx, RCCx, FCCU_Fx,
FAULT-if). An external (to the FCCU) monitor of the IRCOSC clocks and an external reaction
(‘functional’ reset to the MC_RGM) is required to cover potential fault on the IRCOSC clocks.
Self checking capabilities cover the HW reaction of the FCCU due to the assertion of an external fault. The
register interface and the handshake modules are not covered by self-checking capabilities. Any operation
executed by SW (configuration, fault recovery) must be cross-verified by redundancy checks via SW
(registers read following a write/clear operation, internal FCCU state, and so on).
A typical sequence with self checking failure and related reaction is given in Figure 22-27.
SW clear
chip mode
RUN
FCCU SC state
OK
NOK
OK
RCCx interrupt request
Figure 22-27. Self-checking reaction
22.7.4 Reset interface
The FCCU has two input resets and two output resets related to the FAULT state.
Table 22-26. Reset sources
Reset source
External reset
POR
STCU
‘Functional’ reset
‘Destructive’ reset
Support
enabled
enabled
enabled
disabled
enabled
22.7.5 Fault priority scheme and nesting
The FAULT state has a higher priority than the ALARM state in case of concurrent fault events (critical
and non-critical) that occur in the NORMAL state. In case of concurrent critical faults, the fault reaction
corresponds to the worst case (that is, a long ‘functional’ reset is asserted in case it has been programmed).
The ALARM to FAULT state transition occurs if a critical fault or a non-critical fault (unmasked and with
time-out disabled) is asserted in the ALARM state.
Any critical fault (programmed to react with a hard or soft reaction) that occurs when the FCCU is already
in the FAULT state causes an immediate hard or soft reaction (long or short ‘functional’ reset).
22-32
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor