PXS20RM Datasheet, PDF (586/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
forwarded to the AHB upon completion, typically incurring multiple wait-states at the maximum operating
frequency.
The PFLASH2P module supports SoC designs based on a AHB system bus. In particular, this memory
controller is designed to support multiple core designs such as those that include an I/O processor. The
design of the line buffers can accommodate processor cores with or without caches.
23.2.1.1 Features
The following list summarizes the key features of the PFLASH2P:
• The PFLASH2P has two AHB ports with buffering and arbitration logic to efficiently share a single
flash array in a multi-core system.
• The PFLASH2P system bus AHB interfaces support 64-bit data buses. All AHB aligned and
unaligned reads are supported.Only aligned word and doubleword writes are supported.
• The PFLASH2P array interface supports a 128-bit read data bus a 64-bit write data bus.
• The PFLASH2P provides configurable, independent read buffering for each AHB port. There are
four line read buffers and a prefetch controller for each port. The buffers implement a
least-recently-used replacement algorithm to maximize performance. The nomenclature “page
buffers and “line buffers” are used interchangeably.
• The PFLASH2P provides read and write access protections on a per master basis.
• The PFLASH2P provides configurable access timing allowing use in a wide range of platforms and
frequencies.
• The PFLASH2P provides multiple-mapping support and mapping-based block access timing
allowing use for emulation of other memory types.
• The PFLASH2P uses one single asynchronous reset and one global clock.
• The PFLASH2P is implemented using a pos-edge, fully-synthesizable methodology, and uses a
muxed-DFF scan methodology for testability.
23.2.1.2 Block Diagrams
Figure 23-22 provides a system block diagram showing a dual ported flash controller and Figure 23-23 is
a high-level block diagram for the PFLASH2P module.
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor