PXS20RM Datasheet, PDF (413/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
19.2.1.12 eDMA Clear DONE Status (DMACDNE) Register
The DMACDNE register provides a simple memory-mapped mechanism to clear the DONE bit in the
TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding
Transfer Control Descriptor to be cleared. A data value of 64 to 127 (regardless of the number of
implemented channels) provides a global clear function, forcing all DONE bits to be cleared. If the NOP
bit is set, the command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads
of this register return all zeroes.
See Table 19-35 for the TCD DONE bit definition.
Register address: DMA_Offset + 0x001F
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
CDNE
RESET:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-13. eDMA Clear DONE Status (DMACDNE) Register
Name
NOP
CDNE
Table 19-20. DMACDNE field descriptions
Description
Value
No Operation
Clear DONE Status Bit
0 Normal operation
1 No operation, ignore the other bits in the register
See the field structure in Table 19-21
Bit number
0
1–2
3–6
Table 19-21. DMACDNE[CDNE] field structure
Description
“Clear all” bit:
0 Affects only the channel specified in bit numbers 4–7
1 Affects all channels (bit numbers 4–7 are ignored)
Reserved
Clear the corresponding channel’s DONE bit
19.2.1.13 eDMA Interrupt Request Low (DMAINTL) Register
The DMAINTL register provides a bit map for the implemented channels signaling the presence of an
interrupt request for each channel. The eDMA engine signals the occurrence of a programmed interrupt
upon the completion of a data transfer as defined in the transfer control descriptor by setting the
appropriate bit in this register. The outputs of this register are directly routed to the platform’s interrupt
controller. During the execution of the interrupt service routine associated with any given channel, it is
software’s responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to
the DMACINT register in the interrupt service routine is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the DMACINT register. On writes to the DMAINTL, a one in any bit position clears
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
19-17