PXS20RM Datasheet, PDF (685/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
• 01 = Master reload from submodule 0 causes initialization. This setting should not be used in
submodule 0 as it will force the INIT signal to logic 0.
• 10 = Master sync from submodule 0 causes initialization. This setting should not be used in
submodule 0 as it will force the INIT signal to logic 0.
• 11 = EXT_SYNC causes initialization.
FRCEN - Force Initialization Enable
This bit allows the FORCE_OUT signal to initialize the counter without regard to the signal selected
by INIT_SEL. This is a software controlled initialization.
1 = Initialization from a Force Out event is enabled.
0 = Initialization from a Force Out event is disabled.
FORCE - Force Initialization
If the FORCE_SEL bits are set to 000, writing a 1 to this bit results in a Force Out event. This causes
the following actions to be taken:
• The PWMA and PWMB output pins will assume values based on the SEL23 and SEL45 bits.
• If the FRCEN bit is set, the counter value will be initialized with the INIT register value.
FORCE_SEL - Force Source Select
This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
• 000 = The local force signal, FORCE, from this submodule is used to force updates.
• 001 = The master force signal from submodule 0 is used to force updates. This setting should not
be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
• 010 = The local reload signal from this submodule is used to force updates.
• 011 = The master reload signal from submodule0 is used to force updates. This setting should not
be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
• 100 = The local sync signal from this submodule is used to force updates.
• 101 = The master sync signal from submodule0 is used to force updates. This setting should not
be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
• 110 = The external force signal, EXT_FORCE, from outside the PWM module causes updates.
• 111 = reserved
RELOAD_SEL - Reload Source Select
This read/write bit determines the source of the RELOAD signal for this submodule. When this bit is
set, the LDOK bit in submodule 0 should be used since the local LDOK bit will be ignored.
1 = The master RELOAD signal (from submodule 0) is used to reload registers. This setting should
not be used in submodule 0 as it will force the RELOAD signal to logic 0.
0 = The local RELOAD signal is used to reload registers.
CLK_SEL - Clock Source Select
These read/write bits determine the source of the clock signal for this submodule.
• 00 = The IPBus clock is used as the clock for the local prescaler and counter.
• 01 = EXT_CLK is used as the clock for the local prescaler and counter.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
25-39