PXS20RM Datasheet, PDF (1364/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Wakeup Unit (WKPU)
CPU
Destination
Wakeup Enable
Flag
Overrun
Edge Detect
Glitch Filter
NMI
NMI Configuration Register (NCR)
Figure 51-5. NMI pad diagram
51.4.2.1 NMI management
The NMI can be enabled or disabled as required by the application. This can be performed using the single
NCR register laid out to contain all configuration bits in a single byte (see Figure 51-4). The NMI pin can
be configured by the user to recognize interrupts with an active rising edge, an active falling edge or both
edges being active. A setting of having both edge events disabled results in no interrupt being detected and
should not be configured.
The active NMI edge is controlled by the user through the configuration of the NREE and NFEE bits.
NOTE
After reset, NREE and NFEE are set to ‘0’, therefore the NMI functionality
is disabled after reset and must be enabled explicitly by software.
The NMI destination interrupt is controlled by the user through the configuration of the NDSS bits. See
Table 51-3 for details.
The NMI supports a status flag and an overrun flag which are located in the NSR register (see Figure 51-3).
This register is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags in the
same register. The status flag is set whenever an NMI event is detected. The overrun flag is set whenever
an NMI event is detected and the status flag is set (i.e. has not yet been cleared).
51-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor