PXS20RM Datasheet, PDF (192/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
9.3.17.15 Self Test Analog Watchdog Register 3 (STAW3R)
Address: Base + 0x390
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{AW WDT} 0 0
W ^{DE E}
THRH
Reset 0 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0
W
THRL
Reset 0 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1
Figure 9-39. Self Test Analog Watchdog Register 3 (STAW3R)
Table 9-41. STAW3R field descriptions
Field
AWDE
WDTE
THRH
THRL
Description
Analog watchdog enable
0 The analog watchdog related to the algorithm RC is disabled
1 The analog watchdog related to the algorithm RC is enabled
Watchdog timer enable. The watchdog timer verifies:
• Correct sequence of the algorithm (step sequence)
• Execution of the algorithm within the safe time period as defined by STBRR[WDT]
As soon as the watchdog timer is enabled the algorithm starting must be detected within the
safe time period. The watchdog timer is reset each time the algorithm restarts.
Note: This bit should be set only in scan mode.
0 The watchdog timer related to the algorithm RC is disabled
1 The watchdog timer related to the algorithm RC is enabled
High threshold value for channel n. If the analog watchdog is enabled, the STSR1[ERRn]
status bit is set if STDR1[TCDATA] > THRH.
Low threshold value for channel n. If the analog watchdog is enabled, the STSR1[ERRn]
status bit is set if STDR1[TCDATA] < THRH.
9.3.17.16 Self Test Analog Watchdog Register 4 (STAW4R)
Address: Base + 0x394
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{AW WDT} 0 0
W ^{DE E}
THRH
Reset 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0
W
THRL
Reset 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0
Figure 9-40. Self Test Analog Watchdog Register 4 (STAW4R)
9-34
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor