PXS20RM Datasheet, PDF (1254/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Reset Generation Module (MC_RGM)
— VREG and 16 MHz internal RC oscillator stabilization
• a minimum of 3 16 MHz internal RC oscillator clock cycles have elapsed since power-up
completion and the last enabled ‘destructive’ reset event
41.4.1.2 PHASE1 Phase
This phase is entered either on exit from PHASE0 or immediately from PHASE2, PHASE3, or IDLE
on a non-masked external or ‘functional’ reset event if it has not been configured to trigger a ‘short’
sequence. The reset state machine exits PHASE1 and enters PHASE2 on verification of the following:
• all enabled, non-shortened ‘functional’ resets have been processed
• a minimum of 350 16 MHz internal RC oscillator clock cycles have elapsed since the last enabled
external or non-shortened ‘functional’ reset event
41.4.1.3 PHASE2 Phase
This phase is entered on exit from PHASE1. The reset state machine exits PHASE2 and enters PHASE3
on verification of the following:
• all processes that need to be done in PHASE2 are completed
— flash initialization
• a minimum of 8 16 MHz internal RC oscillator clock cycles have elapsed since entering PHASE2
41.4.1.4 PHASE3 Phase
This phase is a entered either on exit from PHASE2 or immediately from IDLE on an enabled, shortened
‘functional’ reset event. The reset state machine exits PHASE3 and enters IDLE on verification of the
following:
• all processes that need to be done in PHASE3 are completed
— trimming, self-test configuration, and FCCU initialization
• a minimum of 40 16 MHz internal RC oscillator clock cycles have elapsed since the last enabled,
shortened ‘functional’ reset event
41.4.1.5 IDLE Phase
This is the final phase and is entered on exit from PHASE3. When this phase is reached, the MC_RGM
releases control of the system to the platform and waits for new reset events that can trigger a reset
sequence.
The actual MBIST and LBIST execution is performed during this phase. (See Chapter 42, Self-Test
Control Unit (STCU), and Chapter 48, System Status and Configuration Module (SSCM).)
41.4.2 Destructive Resets
A ‘destructive’ reset indicates that an event has occurred after which critical register or memory content
can no longer be guaranteed.
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor