PXS20RM Datasheet, PDF (1128/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Nexus Port Controller (NPC)
asynchronously holding all other Nexus modules in reset as well. This prevents Nexus read/write to
memory mapped resources and the transmission of Nexus trace messages.
34.2.3.6 Nexus Double Data Rate Mode
Nexus double data rate (DDR) mode is enabled by asserting the DDR_EN bit in the PCR. In double data
rate mode, message data is updated as follows, effectively doubling message throughput:
• For cut1: On each edge (both rising and falling) of MCKO
• For cut2/3: Between the edges (both rising and falling) of MCKO
34.3 External signal description
34.3.1 Overview
The NPC pin interface provides for the transmission of messages from Nexus blocks to the external
development tools and for access to Nexus client registers. The NPC pin definition is outlined in
Table 34-2.
Table 34-2. NPC Signal Properties
Name
Port
Function
Reset State
Pull¹
EVTO
JCOMP
MDO
MSEO
TCK³
TDI
TDO
TMS
RDY
Auxiliary
JTAG
Auxiliary
Auxiliary
JTAG
JTAG
JTAG
JTAG
JTAG
Event Out pin
JTAG Compliancy and TAP Sharing Control
Message Data Out pins
Message Start/End Out pins
Test Clock Input
Test Data Input
Test Data Output
Test Mode Select Input
Data ready for transfer to/from NRRs
0b1
—
0²
0b11
—
—
High Z⁴
—
—
—
Down
—
—
Down
Up
—
Up
—
NOTES:
1 _{The pull is not implemented in this block. Pullup/pulldown devices are implemented in the pads.}
2 _{Following a power-on reset, MDO[0] remains asserted until power-on reset is exited and the system clock}
achieves lock.
3 _{TCK frequency must be lower than system clock frequency during low power and normal operation modes for}
communication
4 _{TDO output buffer enable is negated when the NPC is not in the Shift-IR or Shift-DR states. A weak pull may}
be implemented on TDO at the SoC level.
34.3.2 Detailed signal descriptions
This section describes each of the signals listed in Table 34-2 in more detail. The JTAG test clock (TCK)
input from the pin is not a direct input to the NPC. The NPC requires two separate input clocks for TCK
clocked logic, one for posedge (rising edge TCK) logic and one for negedge (falling edge TCK) logic. Both
clocks are derived from the pin TCK, and generated external to the NPC.
34-4
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor