PXS20RM Datasheet, PDF (475/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Chapter 21
Error Correction Status Module (ECSM)
21.1 Introduction
The Error Correction Status Module (ECSM) provides miscellaneous control functions for the device
Standard Product Platform (SPP) including program-visible information about the platform configuration
and revision levels, a reset status register, and wakeup control for exiting sleep modes, and optional
features such as information on memory errors reported by error-correcting codes.
21.2 Overview
The Error Correction Status Module is mapped into the IPS space and supports a number of miscellaneous
control functions for the platform device.
21.3 Features
The ECSM includes these features:
• Program-visible information on the platform device configuration and revision
• Reset status register (MRSR)
• Registers for capturing information on platform memory errors if error-correcting codes (ECC) are
implemented
• Registers to specify the generation of single- and double-bit memory data inversions for test
purposes if error-correcting codes are implemented
21.4 Memory map and register description
This section details the programming model for the Error Correction Status Module. This is an on-platform
128-byte space mapped to the region serviced by an IPS bus controller. Some of the control registers have
a 64-bit width. These 64-bit registers are implemented as two 32-bit registers, and include an “H” and “L”
suffixes, indicating the “high” and “low” portions of the control function.
The Error Correction Status Module does not include any logic which provides access control. Rather, this
function is supported using the standard access control logic provided by the IPS controller.
21.4.1 Memory map
Table 21-1 is a 32-bit view of the ECSM’s memory map. The addresses presented here are the offsets
relative to the controller base address 0xFFF4_0000. In DPM, ECSM_1 is located at base address
0x8FF4_0000.
Table 21-1. ECSM memory map
ECSM offset
0x0000
Processor Core Type (PCT)
Register
Chip-defined Platform Revision (PLREV)
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
21-1