PXS20RM Datasheet, PDF (125/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Chapter 4
Operating Modes
Operating Modes
4.1 Overview
PXS20 devices can operate in two modes of operation:
• Lock Step Mode (LSM)
• Decoupled Parallel Mode (DPM)
One of these two operating modes is statically selected at power-up (see Section 4.4, Selecting LSM or
DPM). The selected operating mode may be changed only when going through a full power-on reset.
Both operating mode support a number of chip modes which are controlled by the Mode Entry Module
(MC_ME). These chip modes differ from one another in:
• Which peripherals are enabled
• How the pins are configured
• How the clocks are configured
• Their relative safety status
• Their relative power consumption
See Section 32.1, Introduction, for a complete description of the chip modes.
4.2 Lock Step Mode (LSM)
This operating mode takes its name from the execution of the same commands by both cores in
synchronicity (lock step). It has been implemented to allow reaching SIL3 with minimal software
overhead and is the only operating mode of PXS20 for which a SIL3 capability certificate has been
planned.
In LSM, the Sphere of Replication (SoR) plays a major role. It contains all hardware elements which have
been replicated for safety reasons resulting in the SoR being a collection of pairs. Each member of such a
pair will execute the same operations or transactions as its partner resulting in lock step behavior. The
compliance with this behavior expectation is checked only on the boundary of the SoR, minimizing
checker effort.
This boundary check is based on a modified version of the fault isolation concept. Fault isolation requires
that a fault must not cause failures outside a marked area, in this case the SoR. A failure in the SoR, as long
as it does not propagate to the outside of the SoR and potentially cause a fault there, does not influence the
effective operability of the periphery (and so the ECU). Thus it can not cause a hazard.
For example, an error in the ALU can cause wrong calculation results but as long as these results only
influence core register values, they are not a hazard to the operation of the system. Also, propagation inside
the SoR is of no immediate consequence, e.g. if the wrong register value is written to the INTC, this —
in itself — will not change the overall behavior of the system. But once the registers are written
somewhere external or used as addresses, or once the badly changed interrupt triggers, this 'safeness'
changes because the failure now propagates to the outside of the SoR.
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
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