PXS20RM Datasheet, PDF (318/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Crossbar Switch (XBAR)
15.4.4.4.5 Slave Port State Machine Halt Mode
If the max_halt_request input is asserted the slave port will eventually halt all slave bus activity and go
into halt mode, which is almost identical to low power park mode. The HLP bit in the GPCR controls the
priority level of the max_halt_request in the arbitration algorithm. If the HLP bit is cleared then the
max_halt_request will have the highest priority of any master and will gain control of the slave port at
the next arbitration point (most likely the next bus cycle, unless the current master is running a locked or
fixed length burst transfer). If the HLP bit is set then the slave port will wait until no masters are actively
making requests before moving to halt mode.
Regardless of the state of the HLP bit, once the slave port has gone into halt mode as a result of
max_halt_request being asserted, it will remain in halt mode until max_halt_request is negated,
regardless of the priority level of any masters that may make requests.
In halt mode no master is selected to own the slave port so all the outputs of the slave port are set to 0.
15.5 Initialization/Application Information
No initialization is required by or for the XBAR. Hardware reset ensures all the register bits used by the
XBAR are properly initialized.
15.6 Interface
This section provides information on the XBAR interface.
15.6.1 Overview
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to
communicate in parallel with multiple slaves. In order to maximize data throughput it is essential to keep
arbitration delays to a minimum.
This section examines data throughput from the point of view of masters and slaves, detailing when the
XBAR will stall the masters or insert bubbles on the slave side.
15.6.2 Master Ports
Master accesses will receive one of four responses from the XBAR. They will either be ignored,
terminated, taken, stalled or responded to with an error.
15.6.2.1 Ignored Accesses
A master access will be ignored if the hsel input of the XBAR is not asserted. The XBAR will respond to
IDLE transfers when the hsel input is asserted but will not allow the access to pass through the XBAR.
15.6.2.2 Terminated Accesses
A master access will be terminated if the hsel input of the XBAR is asserted and the transfer type is IDLE.
The XBAR will terminated the access and it will not be allowed to pass through the XBAR.
15-24
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor