PXS20RM Datasheet, PDF (335/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Field
CSSCK
ASC
DT
BR
Table 16-6. DSPI_CTARn field descriptions in master mode (continued)
Descriptions
PCS to SCK Delay Scaler. The CSSCK field selects the scaler value for the PCS to SCK delay. This
field is only used in master mode. The PCS to SCK Delay (t_CSC) is the delay between the assertion
of PCS and the first edge of the SCK. Table 16-8 list the scaler values.The PCS to SCK Delay is a
multiple of the system clock period and it is computed according to the following equation:
t_CSC
=
----1-----  PCSSCK  CSSCK
f_SYS
See Section 16.4.3.2, PCS to SCK Delay (tCSC), for more details.
Eqn. 16-1
After SCK Delay Scaler. The ASC field selects the scaler value for the After SCK Delay. This field is
only used in master mode. The After SCK Delay (t_ASC) is the delay between the last edge of SCK and
the negation of PCS. Table 16-8 list the scaler values.The After SCK Delay is a multiple of the system
clock period, and it is computed according to the following equation:
t_ASC
=
----1-----
f_SYS

PA
SC

A
SC
See Section 16.4.3.3, After SCK Delay (tASC), for more details.
Eqn. 16-2
Delay after Transfer Scaler. The DT field selects the Delay after Transfer Scaler. This field is only used
in master mode. The Delay after Transfer (t_DT) is the time between the negation of the PCS signal at
the end of a frame and the assertion of PCS at the beginning of the next frame. Table 16-8 lists the
scaler values.
In the Continuous Serial Communications Clock operation the DT value is fixed to one SCK clock
period, The Delay after Transfer is a multiple of the system clock period and it is computed according
to the following equation:
t_DT
=
----1-----
f_SYS

PDT

D
T
See Section 16.4.3.4, Delay after Transfer (tDT), for more details.
Eqn. 16-3
Baud Rate Scaler. The BR field selects the scaler value for the baud rate. This field is only used in
master mode. The prescaled system clock is divided by the Baud Rate Scaler to generate the
frequency of the SCK. Table 16-9 lists the Baud Rate Scaler values.The baud rate is computed
according to the following equation:
SCK baud rate = -^f--^S---^Y---^S--  ^{1-----+-----D}-----^B----^R--
PBR BR
See Section 16.4.3.1, Baud rate generator, for more details.
Eqn. 16-4
DBR
0
1
1
1
1
Table 16-7. DSPI SCK Duty Cycle
CPHA
any
0
0
0
0
PBR
any
00
01
10
11
SCK Duty Cycle
50/50
50/50
33/66
40/60
43/57
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-15