PXS20RM Datasheet, PDF (736/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
Field
FAFBIF
FAFAIF
RBIF
TBIF
MIE
PRIE
CHIE
Table 26-17. FR_GIFER field descriptions (continued)
Description
Receive FIFO Channel B Almost Full Interrupt Flag — This flag is set when one of the following
events occurs
a) the current number of FIFO B entries is equal to or greater than the watermark defined by the
WM field in the Receive FIFO Watermark and Selection Register (FR_RFWMSR), and the CC
writes a received message into the FIFO B, or
b) the current number of FIFO B entries is at least 1 and the periodic timer as defined by Receive
FIFO Periodic Timer Register (FR_RFPTR) expires.
0 No such event
1 FIFO B almost full event has occurred
Receive FIFO Channel A Almost Full Interrupt Flag — This flag is set when one of the following
events occurs
a) the current number of FIFO A entries is equal to or greater than the watermark defined by the
WM field in the Receive FIFO Watermark and Selection Register (FR_RFWMSR), and the CC
writes a received message into the FIFO A, or
b) the current number of FIFO B entries is at least 1 and the periodic timer as defined by Receive
FIFO Periodic Timer Register (FR_RFPTR) expires.
0 no such event
1 FIFO A almost full event has occurred
Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual
receive message buffers (FR_MBCCSRn[MTD] = 0) both the interrupt flag MBIF and the interrupt
enable bit MBIE in the corresponding Message Buffer Configuration, Control, Status Registers
(FR_MBCCSRn) are asserted. The application can not clear this RBIF flag directly. This flag is
cleared by the CC when all of the interrupt flags MBIF of the individual receive message buffers
are cleared by the application or if the application has cleared the interrupt enables bit MBIE.
0 None of the individual receive message buffers has the MBIF and MBIE flag asserted.
1 At least one individual receive message buffer has the MBIF and MBIE flag asserted.
Transmit Message Buffer Interrupt Flag — This flag is set if for at least one of the individual
single or double transmit message buffers (FR_MBCCSRn[MTD] = 1) both the interrupt flag MBIF
and the interrupt enable bit MBIE in the corresponding Message Buffer Configuration, Control,
Status Registers (FR_MBCCSRn) are equal to 1. The application can not clear this TBIF flag
directly. This flag is cleared by the CC when either all of the individual interrupt flags MBIF of the
individual transmit message buffers are cleared by the application or the host has cleared the
interrupt enables bit MBIE.
0 None of the individual transmit message buffers has the MBIF and MBIE flag asserted.
1 At least one individual transmit message buffer has the MBIF and MBIE flag asserted.
Module Interrupt Enable — This flag controls if the Module Interrupt line is asserted when the
MIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
Protocol Interrupt Enable — This flag controls if the Protocol Interrupt line is asserted when the
PRIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
CHI Interrupt Enable — This flag controls if the CHI Interrupt line is asserted when the CHIF flag
is set.
0 Disable interrupt line
1 Enable interrupt line
26-24
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor