PXS20RM Datasheet, PDF (209/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
• After first chain conversion ends, STEP0 of algorithm S is executed. Assume the start of STEP0
to be ‘t1’.
• After this STEP1 and STEP2 of algorithm S are executed.
• Then, next chain conversions are performed.
• When chain conversion completes, STEP0 of RC algorithm is performed.
• After each chain conversion, consecutive STEP of RC algorithm is performed. Similar sequence
follows for C algorithm.
• After the last step of C algorithm is performed, another chain conversion is executed. At the end
of this chain conversion, STEP0 of algorithm S is started repeating the whole sequence. Lets
assume this time (starting of STEP0) to be ‘t2’.
• For S algorithm, if (t1 – t0) > Safe Period or (t2 – t1) > Safe Period, Watchdog timer flags an error
and STSR1.WDTERR bit is set. Crictical fault is asserted and interrupt is also generated if enabled
by STCR2.MSKWDTERR bit. Otherwise, watchdog timer counter is reset and starts again to
monitor the same for the next sequence.
• Similar sequence is followed for watchdog timers for RC and C algorithms.
As CTU does not incorporate any safe period checking mechanism, the Watchdog timers can be enabled
for CTU conversions also.
NOTE
You must not enable the watchdog timer for the algorithm which is not to be
executed.
9.4.11.6.1 Watchdog sequence checking
The watchdog timer also incorporates sequence checking features which checks that the steps of a
particular algorithm are in correct order. If steps are not in order, then error is flagged by setting
STSR1[WDSERR]. Crictical fault is asserted and interrupt is also generated if enabled by
STCR2[MSKWDSERR].
Watchdog sequence error is flagged in following cases:
• If steps of any algorithm are not executed in proper order.
• If abort chain occurs during test channel conversion, that step has to be repeated at the end of next
chain. This will give a sequence error as soon as test channel conversion starts again.
Exception : If abort chain occurs during last step of Alg-S, then sequence error is not flagged as the
whole algorithm has to be repeated again.
• If, for CTU conversions, Step Numbers provided by CTU are not in order. Watchdog sequence
checking is significant for CTU burst mode only.
If injected conversion occurs during the test channel, Watchdog sequence error is NOT flagged although
the ongoing Step number is aborted and is repeated again.
Watchdog Timer feature is applicable only for scan mode of operation and not for one shot mode.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
9-51