PXS20RM Datasheet, PDF (211/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Chapter 10
Clock Architecture
Clock Architecture
10.1 Clock generation
The clock generation for this device is illustrated in Figure 10-1.
16 MHz
RC-oscillator
(IRCOSC)
IRCOSC_CLK
4 MHz–16 MHz
40 MHz
Oscillator XOSC_CLK
(XOSC)
MC_CGM
AUX Clock
Selector 3
AUX Clock
Selector 4
PHI_PCS ^{FMPLL_0_PCS_CLK}
FMPLL_0
PHI ^FMPLL_0_CLK
PHI
FMPLL_1
FVCO6
FMPLL_1D0_CLK
FMPLL_1D1_CLK
MC_CGM
IRCOSC_CLK
MC_CGM
SoR_Part_0_CLK
SoR_Part_1_CLK
SYS_CLK
1, 2, 3, ... 16 ^{Peripheral set 0 clock}
System clock divider 0
1, 2, 4, 8
ClockOut_Divider
Clockout
 30 MHz
50%
CMU_0
CMU_1
1, 2, 3, ... 16 ^{Motor control clock}
Auxiliary clock 0 divider 0
1, 2, 3, ... 16 ^{SWG clock}
Auxiliary clock 0 divider 1
1, 2, 3, ... 16 ^{FlexRay clock}
Auxiliary clock 1 divider 0
Legend:
Buffer
Clock gate
CMU_2
1, 2, 3, ... 16 ^{FlexCAN clock}
Auxiliary clock 2 divider 0
XOSC_CLK
Figure 10-1. System clock generation
10.2 Clock distribution
Table 10-1 describes the clock distribution on this chip.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
10-1