PXS20RM Datasheet, PDF (1025/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Offsets: 0x4C–0x88 (16 registers)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
DFL¹
W
00
ID¹
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 _{These fields are writable only in Initialization mode (LINCR1[INIT] = 1).}
Figure 31-37. Identifier filter control registers (IFCR0–IFCR15)
Table 31-35. IFCR field descriptions
Field
DFL
DIR
CCS
ID
Description
Data Field Length
This field defines the number of data bytes in the response part of the frame.
Direction
This bit controls the direction of the data field.
0: LINFlexD receives the data and copy them in the BDRL and BDRM registers.
1: LINFlexD transmits the data from the BDRL and BDRM registers.
Classic Checksum
This bit controls the type of checksum applied on the current message.
0: Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification
2.0 and higher.
1: Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and below.
Identifier
Identifier part of the identifier field without the identifier parity.
31.10.21 Global control register (GCR)
This register can be programmed only in Initialization mode. The configuration specified in this register
applies in both LIN and UART modes.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
31-49