PXS20RM Datasheet, PDF (1309/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Software Watchdog Timer (SWT)
45.3.2.7 SWT Service Key Register (SWT_SK)
The SWT Service Key (SWT_SK) register holds the previous (or initial) service key value. This register
is read only if either the SWT_CR[HLK] or SWT_CR[SLK] bits are set.
Offset 0x018
Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
SK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 45-7. SWT Service Key Register (SWT_SK)
Table 45-8. SWT_SK field descriptions
Field
Description
SK Service Key.This field is the previous (or initial) service key value used in keyed service mode. If
SWT_CR[KEY] is set, the next key value to be written to the SWT_SR is (17*SK+3) mod 2¹⁶.
45.4 Functional Description
The SWT is a 32-bit timer designed to enable the system to recover in situations such as software getting
trapped in a loop or if a bus transaction fails to terminate. It includes a control register (SWT_CR), an
interrupt register (SWT_IR), a time-out register (SWT_TO), a window register (SWT_WN), a service
register (SWT_SR), a counter output register (SWT_CO) and a service key register (SWT_SK).
The SWT_CR includes bits to enable the timer, set configuration options and lock configuration of the
module. The watchdog is enabled by setting the SWT_CR[WEN] bit. The reset value of the
SWT_CR[WEN] bit is device specific. If the reset value of this bit is 1, the watchdog starts operation
automatically after reset is released. Some devices can be configured to clear this bit automatically during
the boot process.
The SWT_TO register holds the watchdog time-out period in clock cycles unless the value is less than
0x100 in which case the time-out period is set to 0x100. This time-out period is loaded into an internal
32-bit down counter when the SWT is enabled and each time a valid service operation is performed. The
SWT down counter is always driven by the IRCOSC clock . The reset value of the SWT_TO register is
device specific.
The configuration of the SWT can be locked through use of either a soft lock or a hard lock. In either case,
when locked the SWT_CR, SWT_TO, SWT_WN and SWT_SK registers are read only. The hard lock is
enabled by setting the SWT_CR[HLK] bit which can only be cleared by a reset. The soft lock is enabled
by setting the SWT_CR[SLK] bit and is cleared by writing the unlock sequence to the service register. The
unlock sequence is a write of 0xC520 followed by a write of 0xD928 to the SWT_SR[WSC] field. There
is no timing requirement between the two writes. The unlock sequence logic ignores service sequence
writes and recognizes the 0xC520, 0xD928 sequence regardless of previous writes. The unlock sequence
can be written at any time and does not require the SWT_CR[WEN] bit to be set.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
45-7