PXS20RM Datasheet, PDF (201/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
9.4.7 DMA functionality
A Direct Memory Access (DMA) request can be programmed after the conversion of every channel, by
setting the respective masking bit in the DMAR0 register. The DMA masking registers must be
programmed before starting any conversion.
The DMA transfers can be enabled using the DMAE[DMAEN] bit. When the DMAE[DCLR] bit is set,
the DMA request is cleared on the reading of the register for which DMA transfer has been enabled.
9.4.8 Interrupts
The ADC generates the following maskable interrupt signals:
• EOC (end of conversion) interrupt request
• ECH (end of chain) interrupt request
• JEOC (end of injected conversion) interrupt request
• JECH (end of injected chain) interrupt request
• WDGxL and WDGxH (watchdog threshold) interrupt requests
• REF_RANGE (reference voltage comparison) interrupt request
• Self test interrupts
Interrupts are generated during the conversion process to signal events such as End Of Conversion as
explained in Section 9.3.3.2, Channel Pending Register 0 (CEOCFR0). Two registers named CEOCFR
(Channel Pending Registers) and IMR (Interrupt Mask Register) are provided in order to check and enable
the interrupt requests.
Interrupts can be individually enabled on a channel by channel base by programming the CIMR (Channel
Interrupt Mask Register).
Several Channel Interrupt Pending Registers are also provided in order to signal which of the channels’
measurement has been completed.
The analog watchdog interrupts are managed by two registers:
• Watchdog Threshold Interrupt Status Register (WTISR)
• Watchdog Threshold Interrupt Mask Register (WTIMR)
The watchdog interrupt source sets two pending bits WDGxH and WDGxL in the WTISR for each of the
four channels being monitored.
The CEOCFR contains the interrupt pending request status. If the user wants to clear a particular interrupt
event status, then writing a ‘1’ to the corresponding status bit clears the pending interrupt flag (at this write
operation all the other bits of the CEOCFR must be maintained at ‘0’).
End of conversion interrupts for self test channel is similar to normal conversion channel. Same EOC and
ECH bits for normal conversion are set for self test channel also. Similar to other channels, self test channel
has Channel interrupt pending bit (ST_EOC) present in STSR1 and channel mask bit (MSKST_EOC) in
STCR2 (corresponding to bits for every channel in CEOCFR and CIMR registers). In addition, End of
Algorithm interrupts are also present which are handled by STSR1 and STCR2 registers.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
9-43