PXS20RM Datasheet, PDF (749/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

26.5.2.22 Protocol Status Register 1 (FR_PSR1)
FlexRay Communication Controller
Base + 0x002A
Additional Reset: CSAA, CSP, CPN: RUN Command
Write: Normal Mode
0
1
2
R CSAA CSP 0
W w1c
Reset 0
0
0
3
4
5
6
7
8
9
10
11
12
13
14
15
REMCSAT
CPN HHR FRZ
APTAC
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-22. Protocol Status Register 1 (FR_PSR1)
Table 26-27. FR_PSR1 Field Descriptions
Field
CSAA
CSP
REMCSAT
CPN
HHR
FRZ
APTAC
Description
Cold Start Attempt Aborted Flag — protocol related event: ‘set coldstart abort indicator in CHI’
This flag is set when the CC has aborted a cold start attempt.
0 No such event
1 Cold start attempt aborted
Leading Cold Start Path — This status bit is set when the CC has reached the POC:normal active
state via the leading cold start path. This indicates that this node has started the network
0 No such event
1 POC:normal active reached from POC:startup state via leading cold start path
Remaining Coldstart Attempts — protocol related variable: vRemainingColdstartAttempts
This field provides the number of remaining cold start attempts that the CC will execute.
Leading Cold Start Path Noise — protocol related variable: vPOC!ColdstartNoise
This status bit is set if the CC has reached the POC:normal active state via the leading cold start
path under noise conditions. This indicates there was some activity on the FlexRay bus while the
CC was starting up the cluster.
0 No such event
1 POC:normal active state was reached from POC:startup state via noisy leading cold start path
Host Halt Request Pending — protocol related variable: vPOC!CHIHaltRequest
This status bit is set when CC receives the HALT command from the application via the Protocol
Operation Control Register (FR_POCR). The CC clears this status bit after a hard reset condition
or when the protocol is in the POC:default config state.
0 No such event
1 HALT command received
Freeze Occurred — protocol related variable: vPOC!Freeze
This status bit is set when the CC has reached the POC:halt state due to the host FREEZE
command or due to an internal error condition requiring immediate halt. The CC clears this status
bit after a hard reset condition or when the protocol is in the POC:default config state.
0 No such event
1 Immediate halt due to FREEZE or internal error condition
Allow Passive to Active Counter — protocol related variable: vPOC!vAllowPassivetoActive
This field provides the number of consecutive even/odd communication cycle pairs that have
passed with valid rate and offset correction terms, but the protocol is still in the POC:normal
passive state due to an application configured delay to enter POC:normal active state. This delay
is defined by the allow_passive_to_active field in the Protocol Configuration Register 12
(FR_PCR12).
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-37