PXS20RM Datasheet, PDF (329/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Table 16-3. DSPI_MCR field descriptions
Field
Description
MSTR
Master/Slave Mode Select. The MSTR bit configures the DSPI for either master mode or slave mode.
0 DSPI is in slave mode
1 DSPI is in master mode
CONT_SCKE Continuous SCK Enable. The CONT_SCKE bit enables the Serial Communication Clock (SCK) to run
continuously. See Section 16.4.5, Continuous Serial Communications Clock, for details.
0 Continuous SCK disabled
1 Continuous SCK enabled
DCONF
DSPI Configuration. The DCONF field selects between the three different configurations of the DSPI:
00 SPI
01 Reserved
10 Reserved
11 Reserved
FRZ
Freeze. The FRZ bit enables the DSPI transfers to be stopped on the next frame boundary when the
SoC enters Debug mode.
0 Do not stop serial transfers
1 Stop serial transfers
MTFE
Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used. See
Section 16.4.4.4, Modified SPI Transfer Format (MTFE = 1, CPHA = 1), for more information.
0 Modified SPI transfer format disabled
1 Modified SPI transfer format enabled
PCSSE
Peripheral Chip Select Strobe Enable. The PCSSE bit enables the PCS[5]/PCSS to operate as an
PCS Strobe output signal. See Section 16.4.3.5, Peripheral Chip Select Strobe Enable (PCSS), for
more information.
0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal
1 PCS[5]/PCSS is used as an active-low PCS Strobe signal
ROOE
Receive FIFO Overflow Overwrite Enable. The ROOE bit enables in RX FIFO overflow condition to
ignore the incoming serial data or to overwrite existing data. If the RX FIFO is full and new data is
received, the data from the transfer, generated the overflow, is ignored or shifted in to the shift register.
See Section 16.4.6.6, Receive FIFO Overflow Interrupt Request, for more information.
0 Incoming data is ignored
1 Incoming data is shifted in to the shift register
PCSISx
Peripheral Chip Select Inactive State. The PCSIS bit determines the inactive state of the PCSx signal.
0 The inactive state of PCSx is low
1 The inactive state of PCSx is high
MDIS
Module Disable. The MDIS bit allows the clock to be stopped to the non-memory mapped logic in the
DSPI effectively putting the DSPI in a software controlled power-saving state. See Section 16.4.7,
Power Saving Features, for more information. The reset value of the MDIS bit is parameterized, with
a default reset value of ‘0’.
0 Enable DSPI clocks.
1 Allow external logic to disable DSPI clocks.
DIS_TXF
Disable Transmit FIFO. When DIS_TXF is set, the TX FIFO acts as a single-entry (unit depth) FIFO.
Therefore, serial operation is performed as if the FIFO has only one valid entry space for serial-word
transfer. See Section 16.4.2.3, FIFO Disable Operation, for details.
0 TX FIFO is enabled
1 TX FIFO is disabled
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-9