PXS20RM Datasheet, PDF (1133/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Nexus Port Controller (NPC)
Table 34-5. PCR field descriptions
Name
Description
FPM
Full Port Mode
The value of the FPM bit determines if the auxiliary output port uses the full MDO port or a
reduced MDO port to transmit messages.
1 = All MDO pins are used to transmit messages
0 = A subset of MDO pins are used to transmit messages
MCKO_GT
MCKO Clock Gating Control
This bit is used to enable or disable MCKO clock gating. If clock gating is enabled, the MCKO
clock is gated when the NPC is in enabled mode but not actively transmitting messages on the
auxiliary output port. When clock gating is disabled, MCKO is allowed to run even if no auxiliary
output port messages are being transmitted.
1 = MCKO gating is enabled
0 = MCKO gating is disabled
MCKO_EN
MCKO Enable
This bit enables the MCKO clock to run. When enabled, the frequency of MCKO is determined
by the MCKO_DIV field.
1 = MCKO clock is enabled
0 = MCKO clock is driven to zero
MCKO_DIV
MCKO Division Factor
The value of this signal determines the frequency of MCKO relative to the system clock
frequency when MCKO_EN is asserted. Table 34-6 shows the meaning of MCKO_DIV Values.
In this table, SYS_CLK represents the system clock frequency.
EVT_EN
EVTO/EVTI Enable
This bit enables the EVTO/EVTI port functions.
1 = EVTO/EVTI port enabled
0 = EVTO/EVTI port disabled
DDR_EN
Double Data Rate Mode Enable
This bit enables Nexus double data rate (DDR) mode. In DDR mode, message data is updated
on both rising and falling edges of MCKO, effectively doubling message throughput.
1 = DDR mode enabled
0 = DDR mode disabled
LP_DBG_EN Low Power Debug Enable
This bit enables debug functionality on exit from low power modes on supported devices.
1 = Low power debug enabled
0 = Low power debug disabled
LPn_SYN
Low Power Mode n Synchronization
These bits are used to synchronize the entry into low power modes between the device and
debug tool. Supported devices set these bits before a pending entry into low power mode. After
reading the bit as set, the debug tool then clears the bit to acknowledge to the device that it may
enter the low power mode.
1 = Low power mode entry pending
0 = Low power mode entry acknowledged
PSTAT_EN
Processor Status Mode Enable¹
This bit enables processor status (PSTAT) mode. In PSTAT mode, all auxiliary output port MDO
pins are used to transmit processor status information, and Nexus messaging is unavailable.
1 = PSTAT mode enabled
0 = PSTAT mode disabled
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
34-9