PXS20RM Datasheet, PDF (645/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

NOTE
Unused MB space must not be used as general purpose RAM while
FlexCAN is transmitting and receiving CAN frames.
FlexCAN Module
24.5 Initialization/Application Information
This section provide instructions for initializing the FlexCAN module.
24.5.1 FlexCAN Initialization Sequence
The FlexCAN module may be reset in three ways:
• MCU level hard reset, which resets all memory mapped registers asynchronously
• MCU level soft reset, which resets some of the memory mapped registers synchronously (refer to
Table 24-2 to see what registers are affected by soft reset)
• SOFT_RST bit in MCR, which has the same effect as the MCU level soft reset
Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock
domains. Therefore, it may take some time to fully propagate its effects. The SOFT_RST bit remains
asserted while soft reset is pending, so software can poll this bit to know when the reset has completed.
Also, soft reset can not be applied while clocks are shut down in any of the low power modes. The low
power mode should be exited and the clocks resumed before applying soft reset.
The clock source (CLK_SRC bit) should be selected while the module is in Disable Mode. After the clock
source is selected and the module is enabled (MDIS bit negated), FlexCAN automatically goes to Freeze
Mode. In Freeze Mode, FlexCAN is un-synchronized to the CAN bus, the HALT and FRZ bits in MCR
Register are set, the internal state machines are disabled and the FRZ_ACK and NOT_RDY bits in the
MCR Register are set. The Tx pin is in recessive state and FlexCAN does not initiate any transmission or
reception of CAN frames. Note that the Message Buffers and the Rx Individual Mask Registers are not
affected by reset, so they are not automatically initialized.
For any configuration change/initialization it is required that FlexCAN is put into Freeze Mode (see
Section 24.4.9.1, Freeze Mode). The following is a generic initialization sequence applicable to the
FlexCAN module:
• Initialize the Module Configuration Register
– Enable the individual filtering per MB and reception queue features by setting the BCC bit
– Enable the warning interrupts by setting the WRN_EN bit
– If required, disable frame self reception by setting the SRX_DIS bit
– Enable the FIFO by setting the FEN bit
– Enable the abort mechanism by setting the AEN bit
– Enable the local priority feature by setting the LPRIO_EN bit
• Initialize the Control Register
– Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
24-45