PXS20RM Datasheet, PDF (921/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
time the interrupt request to the processor is asserted. The rest of the handshaking is described in
Section 28.2.1.1, Software Vector Mode.
28.5.3.1.2 End of Interrupt Exception Handler
Before the interrupt exception handling completes, Section 28.4.6, INTC End of Interrupt Register for
Processor 0 (INTC_EOIR_PRC0), must be written. When it is written, the associated LIFO is popped so
that the preempted priority is restored into PRI of the associated INTC_CPR_PRC0. Before it is written,
the peripheral or software settable flag bit must be cleared so that the peripheral or software settable
interrupt request is negated.
NOTE
A store to clear the peripheral or software settable interrupt flag bit which
closely precedes the store to the INTC_EOIR_PRC0 can result in that
peripheral or software settable interrupt request being serviced again. To
prevent this, execute a Power Architecture ISYNC, MSYNC, or MBAR
instruction before the store to the INTC_EOIR_PRC0 as shown in
Section 28.6.2.1, Software vector mode.
When returning from the preemption, the INTC does not search for the peripheral or software settable
interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt
request may no longer even be asserted. When PRI in the associated INTC_CPR_PRC0 is lowered to the
priority of the preempted ISR, the interrupt request for the preempted ISR or any other asserted peripheral
or software settable interrupt request at or below that priority will not cause a preemption. Instead, after
the restoration of the preempted context, the processor will return to the instruction address that it was to
next execute before it was preempted. This next instruction is part of the preempted ISR or the interrupt
exception handler’s prolog or epilog.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
28-15