PXS20RM Datasheet, PDF (687/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
HALF - Half Cycle Reload
This read/write bit enables half-cycle reloads. A half cycle is defined by when the submodule counter
matches the VAL0 register and does not have to be half way through the PWM cycle.
1 = Half-cycle reloads enabled.
0 = Half-cycle reloads disabled.
FULL - Full Cycle Reload
This read/write bit enables full-cycle reloads. A full cycle is defined by when the submodule counter
matches the VAL1 register. Either the HALF or FULL bit must be set in order to move the buffered
data into the registers used by the PWM generators. If both the HALF and FULL bits are set, then
reloads can occur twice per cycle.
1 = Full-cycle reloads enabled.
0 = Full-cycle reloads disabled.
DT - Deadtime
These read only bits reflect the sampled values of the PWMX input at the end of each deadtime.
Sampling occurs at the end of deadtime 0 for DT[0] and the end of deadtime 1 for DT[1]. Reset clears
these bits.
PRSC - Prescaler
These buffered read/write bits select the divide ratio of the PWM clock frequency selected by
CLK_SEL as illustrated in Table 25-5.
Table 25-5. PWM Prescaler
PRSC
000
001
010
011
100
101
110
111
PWM clock frequency
f_clk
f_clk/2
f_clk/4
f_clk/8
f_clk/16
f_clk/32
f_clk/64
f_clk/128
NOTE
Reading the PRSCx bits reads the buffered values and not necessarily the
values currently in effect. The PRSCx bits take effect at the beginning of the
next PWM cycle and only when the load okay bit, LDOK, is set or LDMOD
is set. This field cannot be written when LDOK is set.
LDMOD - Load Mode Select
This read/write bit selects the timing of loading the buffered registers for this submodule.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
25-41