PXS20RM Datasheet, PDF (614/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexCAN Module
SLF_WAK — Self Wake Up
This bit enables the Self Wake Up feature when FlexCAN is in Stop Mode. If this bit had been asserted
by the time FlexCAN entered Stop Mode, then FlexCAN will look for a recessive to dominant transition
on the bus during these modes. If a transition from recessive to dominant is detected during Stop Mode,
then FlexCAN generates, if enabled to do so, a Wake Up interrupt to the CPU so that it can resume the
clocks globally. This bit can not be written while the module is in Stop Mode.
1 = FlexCAN Self Wake Up feature is enabled
0 = FlexCAN Self Wake Up feature is disabled
WRN_EN — Warning Interrupt Enable
When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error
and Status Register. If WRN_EN is negated, the TWRN_INT and RWRN_INT flags will always be
zero, independent of the values of the error counters, and no warning interrupt will ever be generated.
This bit must be written in Freeze mode only.
1 = TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96
to  96.
0 = TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
LPM_ACK — Low Power Mode Acknowledge
This read-only bit indicates that FlexCAN is either in Disable Mode or Stop Mode. Either of these low
power modes can not be entered until all current transmission or reception processes have finished, so
the CPU can poll the LPM_ACK bit to know when FlexCAN has actually entered low power mode.
See Section 24.4.9.2, Module Disable Mode, and Section 24.4.9.3, Stop Mode, for more information.
1 = FlexCAN is either in Disable Mode or Stop mode
0 = FlexCAN not in any of the low power modes
SRX_DIS — Self Reception Disable
This bit defines whether FlexCAN is allowed to receive frames transmitted by itself. If this bit is
asserted, frames transmitted by the module will not be stored in any MB, regardless if the MB is
programmed with an ID that matches the transmitted frame, and no interrupt flag or interrupt signal
will be generated due to the frame reception. This bit must be written in Freeze mode only.
1 = Self reception disabled
0 = Self reception enabled
BCC — Backwards Compatibility Configuration
This bit is provided to support Backwards Compatibility with previous FlexCAN versions. When this
bit is negated, the following configuration is applied:
• For MCUs supporting individual Rx ID masking, this feature is disabled. Instead of individual ID
masking per MB, FlexCAN uses its previous masking scheme with RXGMASK, RX14MASK and
RX15MASK.
• The reception queue feature is disabled. Upon receiving a message, if the first MB with a matching
ID that is found is still occupied by a previous unread message, FlexCAN will not look for another
matching MB. It will override this MB with the new message and set the CODE field to ‘0110’
(overrun).
24-14
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor