PXS20RM Datasheet, PDF (224/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Generation Module (MC_CGM)
Table 11-5. System Clock Select Status Register (CGM_SC_SS) field descriptions
Field
SELSTAT
Description
System Clock Source Selection Status — This value indicates the current source for the system
clock.
0000 16 MHz int. RC osc.
0001 reserved
0010 4–40 MHz crystal osc.
0011 reserved
0100 system FMPLL
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
11.3.1.4 System Clock Divider Configuration Registers (CGM_SC_DC0)
Address 0xC3FE_037C
Access: User read-only, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
R
0
0
0
DE0
W
DIV0
Reset
1
0
0
0
0
0
0
0
Figure 11-5. System Clock Divider Configuration Registers (CGM_SC_DC0)
This register controls the system clock dividers.
Table 11-6. System Clock Divider Configuration Registers (CGM_SC_DC0) Field Descriptions
Field
Description
DE0
DIV0
Divider 0 Enable
0 Disable system clock divider 0
1 Enable system clock divider 0
Divider 0 Division Value — The resultant peripheral I/O clock will have a period DIV0 + 1 times that of the
system clock. If the DE0 is set to ‘0’ (Divider 0 is disabled), any write access to the DIV0 field is ignored and
the peripheral I/O clock remains disabled.
11-10
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor