PXS20RM Datasheet, PDF (579/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
Table 23-14. UM0 Field Descriptions
Field
Description
0-31 The MISR Registers accumulate a signature from an array integrity event. The MISR captures all data
MISR[31:0] fields, as well as ECC fields, and the read transfer error signal.
The MISR can be seeded to any value by writing the MISR registers.
The MISR register provides a means to calculate a MISR during Array Integrity operations.
The MISR can be represented by the following polynomial:
x¹⁴⁵+ x⁶ + x⁵+ x¹ + 1
The MISR is calculated by taking the previous MISR value and then “exclusive ORing” the new data. In
addition the most significant bit (in this case it is MISR[144]), is then “exclusive ORed” into input of
MISR[6], MISR[5], MISR[1], and MISR[0]. The result of the “exclusive OR” is shifted left on each read.
The MISR register is used in Array Integrity operations.
If during address sequencing, reads extend into an invalid address location (i.e. greater than the
maximum address for a given array size) or locked/unselected blocks, reads are still executed to the array
but the results from the array read are not deterministic. In this instance, the MISR registers are not
recalculated, and the previous value is retained.
After running the user-test-mode margin read (also referenced as factory margin read) sequence on the
C90fl flash module, the MISR registers cannot be written such that the following user-test-mode margin
read sequence cannot seed the MISRs as desired. This will cause the generated MISRs to be
unexpected for the following user margin read sequences, in case customers want to run the user margin
read more than once.
To be able to write the MISR registers:
1) Assert reset after each user margin read sequence so that MISRs can be written again.
2) Do a dummy program to a locked block after user margin read.
23.1.6.12.2 UM1 Register
The following field and bit descriptions fully define the UM1 register (Figure 23-14).
Offset 0x004C
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MISR
W
Reset _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
Figure 23-14. UM1 Register
MISR register functions are shown in Table 23-15.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
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