PXS20RM Datasheet, PDF (410/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
Register address: DMA_Offset + 0x001B
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
CEEI
RESET:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-9. eDMA Clear Enable Error Interrupt (DMACEEI) Register
Name
NOP
CEEI
Table 19-12. DMACEEI field descriptions
Description
No Operation
Clear Enable Error Interrupt
Value
0 Normal operation.
1 No operation, ignore the other bits in the register
See the field structure in Table 19-13
Bit number
0
1–2
3–6
Table 19-13. DMACEEI[CEEI] field structure
Description
“Clear all” bit:
0 Affects only the channel specified in bit numbers 4–7
1 Affects all channels (bit numbers 4–7 are ignored)
Reserved
Clear the corresponding bit in DMAEEIL
19.2.1.9 eDMA Clear Interrupt Request (DMACINT) Register
The DMACINT register provides a simple memory-mapped mechanism to clear a given bit in the
DMAINTL register to disable the interrupt request for a given channel. The given value on a register write
causes the corresponding bit in the DMAINTL register to be cleared. A data value of 64 to 127 (regardless
of the number of implemented channels) provides a global clear function, forcing the entire contents of the
DMAINTL to be zeroed, disabling all eDMA interrupt requests. If the NOP bit is set, the command is
ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all
zeroes.
See Figure 19-10 and Table 19-14 for the DMACINT definition.
Register address: DMA_Offset + 0x001C
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
CINT
RESET:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-10. eDMA Clear Interrupt Request (DMACINT) Register
19-14
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor