PXS20RM Datasheet, PDF (1318/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

System Integration Unit Lite (SIUL)
47.4.1 Detailed signal descriptions
47.4.1.1 General-purpose I/O pins
The GPIO pins provide general-purpose input and output function. The GPIO pins are generally
multiplexed with other I/O pin functions. Each GPIO input and output is separately controlled by an input
(GPDIn_n) or output (GPDOn_n) register. See Section 47.5.2.10, GPIO Pad Data Output Registers
(GPDO) and Section 47.5.2.11, GPIO Pad Data Input Registers (GPDI).
47.4.1.2 External interrupt request input pins (EIRQ[0:31])
The EIRQ[0:31] are connected to the SIU inputs. Rising or falling edge events are enabled by setting the
corresponding bits in the SIU_IREER or the SIU_IFEER register. See Section 47.5.2.5, Interrupt
Rising-Edge Event Enable Register (IREER) and Section 47.5.2.6, Interrupt Falling-Edge Event Enable
Register (IFEER).
47.5 Memory map and register description
This section provides a detailed description of all registers accessible in the SIUL module.
47.5.1 SIUL memory map
Table 47-2 gives an overview on the SIUL registers implemented.
Table 47-2. SIUL memory map
Address offset
Register name
Description
0x0004
0x0008
(0x000C–0x0013)
0x0014
0x0018
(0x001C–0x0027)
0x0028
0x002C
0x0030
(0x0034–0x003F)
0x0040–0x0116
(0x0118–0x04FF)
0x0500–0x0528
(0x052A–0x05FF)
MIDR1
MIDR2
—
ISR
IRER
—
IREER
IFEER
IFER
—
PCR0–PCRn
—
PSMI0_3–
PSMI40_43
—
MCU ID Register #1
MCU ID Register #2
Reserved
Interrupt Status Flag Register
Interrupt Request Enable Register
Reserved
Interrupt Rising Edge Event Enable
Interrupt Falling-Edge Event Enable
IFER Interrupt Filter Enable Register
Reserved
Pad Configuration Registers
Reserved
Pad Selection for Multiplexed Inputs
Reserved
Location
on page 47-6
on page 47-7
on page 47-7
on page 47-8
on page 47-9
on page 47-9
on page 47-10
on page 47-10
on page 47-12
47-4
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor