PXS20RM Datasheet, PDF (926/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
setting its enable bit or disabling the mask bit will cause it to remain negated, which consequently also will
not cause an interrupt request to the processor. Since the ISRs are outside the control of the RTOS, this ISR
will not run unless called by another ISR or the interrupt exception handler, perhaps after executing
another ISR.
28.6.5 Order of Execution
An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors
associated with each of their peripheral or software settable interrupt requests. However, if multiple
peripheral or software settable interrupt requests are asserted, more than one has the highest priority, and
that priority is high enough to cause preemption, the INTC selects the one with the lowest unique vector
regardless of the order in time that they asserted. However, the ability to meet deadlines with this
scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software
settable interrupt requests asserted.
The example in Table 28-3 shows the order of execution of both ISRs with different priorities and the same
priority.
28-20
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor