PXS20RM Datasheet, PDF (746/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.5.2.18 Message Buffer Interrupt Vector Register (FR_MBIVEC)
Base + 0x0022
0
R0
W
Rese
t
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
TBIVEC
00
RBIVEC
000000000000000
Figure 26-18. Message Buffer Interrupt Vector Register (FR_MBIVEC)
This register indicates the lowest numbered receive message buffer and the lowest numbered transmit
message buffer that have their interrupt status flag MBIF and interrupt enable MBIE bits asserted. This
means that message buffers with lower message buffer numbers have higher priority.
Table 26-23. FR_MBIVEC field descriptions
Field
TBIVEC
RBIVEC
Description
Transmit Buffer Interrupt Vector — This field provides the number of the lowest numbered
enabled transmit message buffer that has its interrupt status flag MBIF and its interrupt enable bit
MBIE set. If there is no transmit message buffer with the interrupt status flag MBIF and the interrupt
enable MBIE bits asserted, the value in this field is set to 0.
Receive Buffer Interrupt Vector — This field provides the message buffer number of the lowest
numbered receive message buffer which has its interrupt flag MBIF and its interrupt enable bit
MBIE asserted. If there is no receive message buffer with the interrupt status flag MBIF and the
interrupt enable MBIE bits asserted, the value in this field is set to 0.
26.5.2.19 Channel A Status Error Counter Register (FR_CASERCR)
Base + 0x0024
Additional Reset: RUN Command
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
STATUS_ERR_CNT
W
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-19. Channel A Status Error Counter Register (FR_CASERCR)
This register provides the channel status error counter for channel A. The protocol engine generates a slot
status vector for each static slot, each dynamic slot, the symbol window, and the NIT. The slot status vector
contains the four protocol related error indicator bits vSS!SyntaxError, vSS!ContentError, vSS!BViolation,
and vSS!TxConflict. The CC increments the status error counter by 1 if, for a slot or segment, at least one
error indicator bit is set to 1. The counter wraps around after it has reached the maximum value. For more
information on slot status monitoring, see Section 26.6.18, Slot Status Monitoring.
26-34
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor