PXS20RM Datasheet, PDF (705/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
• 11 = EXTB[0] signal is used by the deadtime logic.
25.4.4.5 Master Control Register (MCTRL)
PWM_BASE
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0
Read
Write
Reset
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IPOL
RUN
0000
CLDOK
LDOK
000000000000000
Figure 25-63. Master Control Register (MCTRL)
IPOL - Current Polarity
This buffered read/write bit is used to select between PWM23 and PWM45 as the source for the
generation of the complementary PWM pair output. IPOL is ignored in independent mode.
1 = PWM45 (Figure 25-2) is used to generate complementary PWM pair.
0 = PWM23 (Figure 25-2) is used to generate complementary PWM pair.
NOTE
The IPOL bit does not take effect until a FORCE_OUT event takes place in
the appropriate submodule. Reading the IPOL bit reads the buffered value
and not necessarily the value currently in effect.
RUN - Run
This read/write bit enables the clocks to the PWM generator. When RUN equals zero, the submodule
counter is reset. In submodules other than 0, the local RUN bit is ignored when CLK_SEL is 1 because
this indicates that the AUX_CLK from submod0 is being used by this submodule. A reset clears RUN.
1 = PWM generator enabled.
0 = PWM generator disabled.
NOTE
For proper initialization of the LDOK and RUN bits, see Section 25.3.4.5,
Initialization.
CLDOK - Clear Load Okay
This write only bit is used to clear the LDOK bit. Write a 1 to this location to clear the corresponding
LDOK. If a reload occurs with LDOK set at the same time that CLDOK is written, then the reload will
not be performed and LDOK will be cleared. This bit is self clearing and always reads as a 0.
LDOK - Load Okay
This read/set bit loads the PRSC bits of CTRL1 and the INIT, FRACx, and VALx registers into a set
of buffers. The buffered prescaler divisor, submodule counter modulus value, and PWM pulse width
take effect at the next PWM reload if LDMOD is clear or immediately if LDMOD is set. Set LDOK
by reading it when it is logic zero and then writing a logic one to it. The VALx, FRACx, INIT, and
PRSC registers cannot be written while LDOK is set. LDOK is automatically cleared after the new
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
25-59